1. Field of the Invention
The present invention relates generally to semiconductor devices, and more particularly, to a deep trench capacitor dynamic random access memory (DRAM) cell and manufacture method thereof.
2. Description of the Prior Art
A memory cell of a DRAM is composed of a metal oxide semiconductor (MOS) transistor connected to a capacitor. The MOS transistor comprises a gate, and a first and second doped regions. The doped regions are used as a source or a drain depending on the operational situation of the MOS transistor. The MOS transistor functions by using the gate electrically connected to a word line as a switch, using the source electrically connected to a bit line as a current transporting path, and using the drain electrically connected to a storage node of the capacitor to complete data accessing.
The capacitor, composed of a top electrode, a capacitor dielectric layer and a storage node, is formed on a silicon oxide layer over a substrate. In a present DRAM process, the capacitor is designed as either a stack capacitor stacked on the substrate or a deep trench capacitor buried within the substrate.
Please refer to FIG. 1 to FIG. 6. FIGS. 1-6 are schematic, cross-sectional diagrams showing a method of fabricating a trench capacitor of a DRAM device according to the prior art method. As shown in FIG. 1, a pad layer 14 composed of a silicon nitride layer and a pad oxide layer is formed on a substrate 12 of a semiconductor wafer. A photoresist layer (not shown) is formed on the surface of the pad layer 14. Next, a photolithographic process and etching process are performed to form an opening 16 in the pad layer 14 to define the position of the deep trench.
As shown in FIG. 2, an etching process is performed using the pad layer 14 as a mask to etch the opening 16 down to the substrate 12 to form a deep trench 18 with a depth of 7-8 micrometers (μm). Subsequently, an arsenic silicate glass (ASG) diffusion method is used to form a N-doped buried plate 20 as a top plate of the capacitor within the substrate 12 and beneath the deep trench 18.
As shown in FIG. 3, a chemical vapor deposition (CVD) process is performed to form a silicon nitride layer (not shown) on the surface of the deep trench 18. Next, a thermal oxidation process is performed to grow an oxide layer (not shown) on the silicon nitride layer, so that the silicon nitride layer together with the oxide layer form a capacitor dielectric layer 22. Next, a N-doped polysilicon layer 24 is deposited into and completely fills in the deep trench 18, to function as a primary conductor of the storage node. A planarization process, such as a chemical mechanical polishing (CMP) or an etching back process, is performed using the pad layer 14 as a stop layer to remove portions of the doped polysilicon layer 24 and align its surface with the pad layer 14.
As shown in FIG. 4, a first polysilicon recess etching process is performed to etch the doped polysilicon layer 24 down to the surface of the substrate 12. A wet etching process is then performed, using phosphoric acid (H3PO4) as the etching solution, to remove about half the depth of the capacitor dielectric layer 22 so as to expose the area of the substrate 12 in the upper region of the deep trench 18.
As shown in FIG. 5, another thermal oxidation process is performed to form a pair of collar oxides 26, with a thickness of 200-300 angstroms, on the exposed substrate 12 in the upper region of the deep trench 18. A N-doped polysilicon layer 27 is deposited on the surface of the semiconductor wafer and fills in the deep trench 18, followed by a planarization process to remove portions of the doped polysilicon layer 27 and approximately align the surface of the doped polysilicon layer 27 with that of the pad layer 14. A second polysilicon recess etching process is performed to etch back portions of the doped polysilicon layer 27 and lower the surface of the remaining doped polysilicon layer 27 down to the surface of the collar oxides 26.
As shown in FIG. 6, an etching process is performed to remove portions of the collar oxides 26 so as to expose the substrate 12 in the deep trench 18. A CVD process is then performed to deposit a polysilicon layer 28 on the semiconductor wafer. Next, a planarization process is performed using the pad layer 14 as a stop layer to remove portions of the polysilicon layer 28 and approximately align the surface of the remaining polysilicon layer 28 with that of the pad layer 14. A third polysilicon recess etching process is performed to etch back the polysilicon layer 28 and lower its surface down to the pad layer 14. Finally, the pad layer 14 is completely removed to finish the fabrication of the storage node.
In the prior art method, a phase-in polysilicon filling is used to fabricate the storage node, which requires a three-time repeated operational cycle of deposition, planarization and recess etching processes. Thus, it not only complicates the fabrication process but also increases both production cost and time. In addition, the prior art trench-capacitor DRAM device has a drawback in that so-called trench induced junction leakage adversely affects data storage and reliability.